Delay control circuits are in widespread use as means for outputting a plurality of clocks having a prescribed delay difference (resolution) with respect to a reference clock signal. One application is a CDR (Clock Data Recovery) circuit characterized by oversampling. It is required that the characteristic of the plurality of clocks used be such that phase difference is not affected by fluctuations in temperature, power supply voltage and discrepancies in process manufacture and such that resolution (power) has a fine value on the order of several tens of picoseconds.
There are instances where a DLL (Delay-Locked Loop) is used as an example of such a delay control circuit. For example, a digital phase control circuit described in Patent Document 1 can be mentioned. FIG. 15 is a circuit diagram of the digital phase control circuit of Patent Document 1. The circuit is composed of a delay-locked loop (DLL1) having a resolution of 160 ps and a delay-locked loop (DLL2) having a resolution of 200 ps.
[Patent Document 1]
Japanese Patent Kokai Publication No. JP-P2001-285266A
[Patent Document 2]
Japanese Patent Kohyo Publication No. JP-A-11-513847